1. Field of the Invention
The present invention is in the field of integrated circuit fabrication. More particularly, the invention is in the field of bonding pad and support structures for integrated circuits using copper and low dielectric constant materials.
2. Background Art
The drive to fabricate faster IC (Integrated Circuit) chips is in large part focused on improving the speed of the IC chip interconnect while maintaining or improving other aspects of IC chip performance such as, low power consumption, low noise, and long term reliability and while maintaining or improving the manufacturing cost. Interconnect delay is directly proportional to the product of interconnect resistance and the capacitance driven by the interconnect. Thus, in order to improve the speed of the IC chip interconnect, there is need to the reduce the resistivity and the capacitance of the IC chip interconnect. The capacitance of the interconnect is directly proportional to the dielectric constant ("k") of the dielectric that insulates the interconnect from other interconnect or other circuits of the IC chip. As such, reducing the dielectric constant of the dielectric results in a reduction of the interconnect capacitance and a reduction in the interconnect delay.
Traditionally, aluminum has been used as the primary interconnect conductor and silicon dioxide has been used as the primary dielectric in IC chips. Recently, copper has become more desirable as an interconnect conductor at least partly due to the fact that copper has lower resistivity than aluminum. Also recently, a number of low dielectric constant ("low-k") materials having dielectric constants below that of silicon dioxide (whose dielectric constant is approximately 4.0) have been used in IC chips. However, the use of copper and a low-k dielectric material has introduced a number of challenges in manufacturing IC chips.
For example, it is difficult to etch copper and as such the "subtractive etch" process used to etch aluminum cannot be successfully used in copper chips. Thus, the present approach to patterning copper interconnect is based on "damascene" processing. The term "damascene" is derived from the ancient in-laid metal artistry originated in Damascus. According to the damascene process, a trench or canal is cut into the dielectric and then filled with metal. FIGS. 1A through 1D help describe an overview of the damascene process used to fabricate copper interconnect.
Referring to FIG. 1A, insulating layer 102 (for example, silicon dioxide) is formed on a substrate 104, which usually contains circuitry and may contain other interconnection levels. To help with the patterning of copper by the damascene process, layer 102 should have a uniform thickness and be as flat as possible. An ideally flat insulating layer 102 is shown in FIG. 1A.
FIG. 1B shows a cross-section of layer 102 after patterning to create two trenches, wide trench 106 and narrow trench 108. These trenches are formed by removing a top portion of layer 102 using photolithography and a suitable anisotropic etch technique, such as reactive ion etching, which are known in the art. These trenches are where copper interconnect conductors should be laid in. Moreover, insulator 107 is to provide insulation between the copper interconnect to be laid in trench 106 and the copper interconnect to be laid in trench 108. Referring to FIG. 1C, copper film 112 is shown as having been deposited over insulating layer 102. Although not shown in any of the Figures, prior to deposition of copper film 112, a metal barrier layer such as tantalum (Ta) or tantalum nitride (TaN) is deposited over insulating layer 102. Copper film 112 may, for example, be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), PVD followed by reflow, or electroplating. Preferably, copper film 112 is deposited to a depth such that trenches 106 and 108 are completely filled with copper. Manifestly, the unwanted portions of copper film 112, for example the portion that is shown as covering insulator barrier 107, must be removed.
FIG. 1D shows a wide inlaid copper conductor 114 and a narrow inlaid copper interconnect 116 remaining in trenches 106 and 108, respectively, after polishing to remove the unwanted portions of copper film 112. Polishing is preferably accomplished by chemical-mechanical polishing (CMP), wherein the semiconductor wafer and/or a polishing pad are rotatably mounted and brought into contact with each other under rotation. A slurry providing both abrasive and chemically reactive components is supplied, typically to the pad, during polishing. The abrasive component is typically comprised of finely ground colloidal silica or alumina particles. The chemically reactive component is typically diluted acid and/or hydrogen peroxide, with the remainder of the slurry comprised of deionized water. In general, it is desirable that the slurry composition and polishing conditions (e.g. rotational velocity, polish force, temperature) be adjusted such that the conducting films (i.e. the deposited copper film and the metal barrier layer) are selectively removed at a faster rate than the insulating layer (30:1 being a typical ratio) during the CMP.
One drawback of the CMP process, however, is illustrated in FIG. 1D. The top surface of narrow copper interconnect 116 is shown as slightly "dished" but substantially co-planar with the upper surface of insulating layer 102. However, wide copper interconnect 114 is shown as severely dished. The dishing phenomenon, such as that shown in wide interconnect 114, results in an uneven profile in the interconnect layer which is harmful to the fabrication process of subsequent layers in the IC chip. In extreme cases, sections of a wide conductor, such as wide conductor 114, may be completely removed from the trench during polishing, leaving the trench bottom exposed. This total absence of any metal at the central parts of a wide metal conductor is undesirable since, for example, it causes an increase in the resistance of the metal interconnect and also reduces the long term reliability of the IC chip.
An additional problem caused by the dishing phenomenon is that vias that are supposed to make electrical connection between a metal layer on top of the wide conductor and the wide conductor may not reach the shallow parts of the wide conductor since the shallow parts have too little metal left and are lower than the remaining portions of the wide interconnect. In other words, while vias from an overlaying metal layer are designed to be long enough to reach the surface of an underlying metal interconnect, the vias over a wide interconnect are too short to reach the "dished" portions of the wide interconnect.
It has been discovered that the dishing during the CMP process may be substantially reduced by having "dielectric fillers" in wide trenches such as trench 106. Generally, experimentation with specific conducting and insulating materials and a desired CMP process is required to determine the minimum line width that is subject to severe dishing and as such would require dielectric fillers to reduce or eliminate such dishing. Typically this width may vary from several microns to tens of microns. However, it is generally understood that a typical bonding pad which has a width of between 60 to 100 microns is clearly wide enough to be subject to dishing as a result of the CMP process. Accordingly, dielectric fillers to reduce or eliminate dishing are conventionally needed for copper bonding pads formed by a damascene process.
Conventional solutions using dielectric fillers to reduce dishing in copper bonding pads are shown in FIGS. 2A and 2B. FIGS. 2A and 2B illustrate use of dielectric fillers with two slightly different configurations. FIG. 2A is a top view of a copper bonding pad 230. Dielectric fillers shaped as long rectangular strips (as viewed from the top of the bonding pad) are distributed within copper bonding pad 230. An example of such rectangular strip dielectric fillers is referred to by numeral 232 in FIG. 2A. FIG. 2B is a top view of a copper bonding pad 240. Dielectric fillers shaped as squares (as viewed from the top of the bonding pad) are distributed within copper bonding pad 240. An example of such square dielectric fillers is referred to by numeral 242 in FIG. 2B.
A side view of copper bonding pad 230 in FIG. 2A along the line marked as 2C (which is the same as a side view of copper bonding pad 240 in FIG. 2B along the line marked as 2C) is shown in FIG. 2C. FIG. 2C shows insulating layer 202 (corresponding to insulating layer 102 in FIGS. 1A through 1D) which rests on substrate 204 (corresponding to substrate 104 in FIGS. 1A through 1D). Trench 206 in FIG. 2C corresponds to trench 106 in FIGS. 1A through 1D while trench 208 in FIG. 2C corresponds to trench 108 in FIGS. 1A through 1D. Dielectric fillers 252 in FIG. 2C are cross-sections of dielectric fillers 232 in FIG. 2A (or dielectric fillers 242 in FIG. 2B). Dielectric fillers 252 in FIG. 2C are located between metal segments 254 in FIG. 2C. Although not apparent from FIG. 2C, metal segments 254 are electrically connected as shown in FIGS. 2A and 2B. In other words, metal segments 254 are part of the same bonding pad 230 in FIG. 2A (or bonding pad 240 in FIG. 2B).
As can be seen from FIG. 2C, narrow conductor 216 (which corresponds to narrow conductor 116 in FIG. 1D) shows only slight dishing. However, wide conductor 214 (corresponding to pad 230 in FIG. 2A or pad 240 in FIG. 2B) also shows slight dishing in metal segments 254 as shown in FIG. 2C. The reduced dishing of wide conductor 214 in FIG. 2C as compared with wide conductor 114 in FIG. 1D is due to the existence of dielectric fillers 252. Dielectric fillers 252 cause metal segments 254 to behave as narrow conductor 216 as concerns the CMP process. Accordingly, the dishing effect in metal segments 254 becomes less severe as is the case for a narrow conductor such as conductor 216.
Although the use of dielectric fillers in copper bonding pads reduces or eliminates the severe dishing problem that would otherwise exist, the dielectric fillers actually impair some of the performance characteristics of the copper bonding pads. For example, dielectric fillers lead to very poor adhesion to the bond wires which are typically made of gold or aluminum. Moreover, since some of the bonding pad is covered by dielectric fillers (which are insulators), the electrical connection between the bond wire and the bonding pad is also impaired. Further, dielectric fillers are also poor thermal conductors and as such reduce the thermal conductivity of the copper bonding pad.
Recently, some IC chip manufacturers have opted not to use dielectric fillers in copper bonding pads in order to avoid the disadvantages introduced by the dielectric fillers. These manufacturers have improved the CMP process such that the dishing problem is reduced, although not entirely eliminated. As a result of the improved CMP process, although some dishing still occurs, the dishing is not severe enough to cause a total removal of the metal from portions of a wide copper conductor.
As stated above, the need to reduce the capacitance in the IC chip interconnect has also resulted in the use of low-k dielectric materials. A low-k dielectric material is used in combination with copper interconnect (in a damascene process) to achieve a reduction in interconnect capacitance. However, low-k dielectric materials further complicate the design of copper bonding pads. Low-k dielectric materials which underlie the copper bonding pad have low mechanical strength. Due to the force applied to attach the bond wire to the bonding pad, low-k materials below the bonding pad may experience cracks. These cracks may cause immediate damage to the neighboring circuits on the IC chip. Alternatively, cracks that are too small for immediate damage may grow and cause long term reliability problems in the IC chip. Therefore, the poor mechanical strength of low-k materials must somehow be circumvented in copper chips using copper bonding pads.
From the above discussion of the background art it is apparent that there is serious need in the art for a copper bonding pad and support structure which provides sufficient mechanical support and strength, exhibits good adhesion to bond wires, maintains a very strong electrical contact with bond wires, has good thermal conductivity, and is not severely affected by the dishing problem existing in damascene and CMP processing.